Maxim DS33Z41 Dokumentacja Pobierz pdf (Strona 13)

Q9. Is it possible to use a sine-wave oscillator instead of a square-wave oscillator to supply

different frequencies at the CLAD for the DS325x?

A9. Yes. It is possible to use a sine-wave oscillator to supply sinusoidal frequencies to the input of the DS325x's CLAD.

The lowest voltage of the sine wave cannot go below the diode drop, and it is recommended that the voltage is a 3.0V

sine wave with minimum of 0V.

Q10. Does the DS26334 LIU support internal impedance-matched operation? If so, what are the

steps to program the device in this mode?

A10. Yes, the DS26334 does support internal impedance-matched operation for devices that are revision A2 or later.

Revision A1 does not support this mode. When the DS26334 is in internal impedance-termination mode, RTIP and RRING

require no external resistance components. However, for better internal resistance accuracy, a 16.5kΩ ±1% resistor is

required on the RESREF pin. For external termination mode, the RESREF pin must be tied to GND. It is also important to

note that, in internal impedance-termination mode, a 1:1 transformer on the receive side is required. If you are using a

1:2 transformer, a 30Ω resistor must be placed in parallel with RRTIP and RRING.

5. BERT Questions

Q1. When using the DS2155, DS2172, or DS2174 bit-error-rate tester (BERT) function with a

pseudorandom bit stream (PRBS) pattern, what status bits must be checked to validate that the

pattern is being correctly received?

A1. Status Register 9 (SR9 in the DS2155) should be checked to ensure that the BERT is in synchronization and that the

device is not receiving an all zero pattern. When properly receiving a PRBS pattern, the synchronization bit (SYNC or

BSYNC in the DS2155) equals 1, and the receive-all-zeros bit (RA0 or BRA0 in the DS2155) equals 0. When receiving a

PRBS pattern, it is important to verify that the receive-all-zeros bit equals 0 because the BERT uses a linear-feedback

shift register (LFSR), which enters a 'dead state' when it receives all zeros. If the receive-all-zeros bit equals 1, it is

possible for the BERT bit counters to begin counting received bits. This would result in the miscalculation of the bit-error

rate. Therefore, the receive-all-zeros bit should be checked whenever receiving a PRBS pattern.

Q2. Why do the DS2172/DS2174 BERT devices remain in synchronization when the clock signal

applied to the receive-clock (RCLK) pin is removed or held in a steady state?

A2. Both the DS2172 and the DS2174 can remain in synchronization when the clock signal applied to the receive-clock

(RCLK) is removed. This reason for this behavior is that the state machine that controls the receive synchronization is

clocked by the signal applied to the receive-clock pin. If the receive-clock signal is removed or held in a steady state, the

data in the status register will no longer get updated. During this time, however, read and write operations will all

continue to operate normally. The easiest method to determine if the signal present on the receive-clock pin is changing

is to read the bit-count registers. If the bit count remains the same with each consecutive read, there is no signal on the

receive-clock pin.

Q3. How is the latch-count (LC) bit used to set the time interval for the bit and error counters of

the DS21372, DS2172, and DS2174?

A3. Both the bit and error counters of the BERT devices contain a second shadow register that is used to latch the current

value. When the LC bit is set from 0 to 1, two events occur. First, the current value of the bit and error counters is

latched in the shadow registers. Second, the bit and error counters are cleared and will resume operation. The software

can then access the shadow registers to read the previous count values. To measure the bit and error counts from time

T0 to T1, the following procedure is necessary:

At time T0, set the LC bit from 0 to 1. This will clear the bit and error counters and latch the previous count values, which

can be discarded. At time T1, set the LC bit from 0 to 1. This will clear the bit and error counters and latch the count

values from time T0 to T1, which the software can access.

Page 13 of 22

1 2 ... 8 9 10 11 12 13 14 15 16 17 18 ... 21 22

Komentarze do niniejszej Instrukcji

Brak uwag

Maxim DS33Z41 Dokumentacja Strona 13

Komentarze do niniejszej Instrukcji

Powiązane produkty i podręczniki dla Networking Maxim DS33Z41