Maxim DS33Z41 Dokumentacja

1 of 167 REV: 122006 Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple re

DS33Z41 Quad IMUX Ethernet Mapper 10 of 167 2.10 Specifications compliance The DS33Z41 meets relevant telecommunications specifications. The follow

DS33Z41 Quad IMUX Ethernet Mapper 100 of 167 Register Name: LI.RMPSCH Register Description: Receive Maximum Packet Size Control High Register Regi

DS33Z41 Quad IMUX Ethernet Mapper 101 of 167 Register Name: LI.RPPSRL Register Description: Receive Packet Processor Status Register Latched Regis

DS33Z41 Quad IMUX Ethernet Mapper 102 of 167 Register Name: LI.RPPSRIE Register Description: Receive Packet Processor Status Register Interrupt En

DS33Z41 Quad IMUX Ethernet Mapper 103 of 167 Register Name: LI.RPCB0 Register Description: Receive Packet Count Byte 0 Register Register Address:

DS33Z41 Quad IMUX Ethernet Mapper 104 of 167 Register Name: LI.RFPCB0 Register Description: Receive FCS Errored Packet Count Byte 0 Register Regi

DS33Z41 Quad IMUX Ethernet Mapper 105 of 167 Register Name: LI.RAPCB0 Register Description: Receive Aborted Packet Count Byte 0 Register Register

DS33Z41 Quad IMUX Ethernet Mapper 106 of 167 Register Name: LI.RSPCB0 Register Description: Receive Size Violation Packet Count Byte 0 Register Re

DS33Z41 Quad IMUX Ethernet Mapper 107 of 167 Register Name: LI.RBC0 Register Description: Receive Byte Count 0 Register Register Address: 118h B

DS33Z41 Quad IMUX Ethernet Mapper 108 of 167 Register Name: LI.RAC0 Register Description: Receive Aborted Byte Count 0 Register Register Address:

DS33Z41 Quad IMUX Ethernet Mapper 109 of 167 Register Name: LI.RHPMUU Register Description: Serial Interface Receive HDLC PMU Update Register Reg

DS33Z41 Quad IMUX Ethernet Mapper 11 of 167 3 APPLICATIONS • Bonded Transparent LAN Service • LAN Extension • Ethernet Delivery Over T1/E1/J1, T

DS33Z41 Quad IMUX Ethernet Mapper 110 of 167 Register Name: LI.RX86LSIE Register Description: Receive X.86 Interrupt Enable Register Address: 123h

DS33Z41 Quad IMUX Ethernet Mapper 111 of 167 Register Name: LI.TQHT Register Description: Serial Interface Transmit Queue High Threshold (Watermar

DS33Z41 Quad IMUX Ethernet Mapper 112 of 167 9.6 Ethernet Interface Registers The Ethernet Interface registers are used to configure RMII/MII bus

DS33Z41 Quad IMUX Ethernet Mapper 113 of 167 Register Name: SU.MACRD1 Register Description: MAC Read Data Byte 1 Register Address: 143h Bit # 7 6

DS33Z41 Quad IMUX Ethernet Mapper 114 of 167 Register Name: SU.MACWD1 Register Description: MAC Write Data Byte 1 Register Address: 147h Bit # 7

DS33Z41 Quad IMUX Ethernet Mapper 115 of 167 Register Name: SU.MACAWH Register Description: MAC Address Write High Register Address: 14Bh Bit #

DS33Z41 Quad IMUX Ethernet Mapper 116 of 167 Register Name: SU.LPBK Register Description: Ethernet Interface Loopback Control Register Register Ad

DS33Z41 Quad IMUX Ethernet Mapper 117 of 167 Register Name: SU.TFRC Register Description: Transmit Frame Resend Control Register Address: 151h Bi

DS33Z41 Quad IMUX Ethernet Mapper 118 of 167 Register Name: SU.TFSL Register Description: Transmit Frame Status Low Register Address: 152h Bit #

DS33Z41 Quad IMUX Ethernet Mapper 119 of 167 Register Name: SU.RFSB0 Register Description: Receive Frame Status Byte 0 Register Address: 154h Bit

DS33Z41 Quad IMUX Ethernet Mapper 12 of 167 4 ACRONYMS AND GLOSSARY • BERT—Bit Error Rate Tester • DCE—Data Communication Interface • DTE—Data

DS33Z41 Quad IMUX Ethernet Mapper 120 of 167 Register Name: SU.RFSB3 Register Description: Receive Frame Status Byte 3 Register Address: 157h Bit

DS33Z41 Quad IMUX Ethernet Mapper 121 of 167 Register Name: SU.RMFSRL Register Description: Receiver Maximum Frame Low Register Register Address:

DS33Z41 Quad IMUX Ethernet Mapper 122 of 167 Register Name: SU.QRIE Register Description: Receive Queue Cross Threshold Enable Register Address: 15

DS33Z41 Quad IMUX Ethernet Mapper 123 of 167 Register Name: SU.RFRC Register Description: Receive Frame Rejection Control Register Address: 15Eh

DS33Z41 Quad IMUX Ethernet Mapper 124 of 167 9.6.2 MAC Registers The control registers related to the control of the individual MACs are shown in t

DS33Z41 Quad IMUX Ethernet Mapper 125 of 167 Bit 12: Late Collision Control (LCC). When set to 1, enables retransmission of a collided packet even

DS33Z41 Quad IMUX Ethernet Mapper 126 of 167 Register Name: SU.MACAH Register Description: MAC Address High Register Register Address: 0004h (indi

DS33Z41 Quad IMUX Ethernet Mapper 127 of 167 Register Name: SU.MACMIIA Register Description: MAC MII Management (MDIO) Address Register Register A

DS33Z41 Quad IMUX Ethernet Mapper 128 of 167 Register Name: SU.MACMIID Register Description: MAC MII (MDIO) Data Register Register Address: 0018h

DS33Z41 Quad IMUX Ethernet Mapper 129 of 167 Register Name: SU.MACFCR Register Description: MAC Flow Control Register Register Address: 001Ch (ind

DS33Z41 Quad IMUX Ethernet Mapper 13 of 167 5 MAJOR OPERATING MODES Operation of the DS33Z41 operation requires a host microprocessor for initiali

DS33Z41 Quad IMUX Ethernet Mapper 130 of 167 Register Name: SU.MMCCTRL Register Description: MAC MMC Control Register Register Address: 0100h (ind

DS33Z41 Quad IMUX Ethernet Mapper 131 of 167 Register Name: Reserved Register Description: MAC Reserved Control Register Register Address: 010Ch (

DS33Z41 Quad IMUX Ethernet Mapper 132 of 167 Register Name: Reserved Register Description: MAC Reserved Control Register Register Address: 0110h (

DS33Z41 Quad IMUX Ethernet Mapper 133 of 167 Register Name: SU.RxFrmCtr Register Description: MAC All Frames Received Counter Register Address: 02

DS33Z41 Quad IMUX Ethernet Mapper 134 of 167 Register Name: SU.RxFrmOkCtr Register Description: MAC Frames Received OK Counter Register Address: 0

DS33Z41 Quad IMUX Ethernet Mapper 135 of 167 Register Name: SU.TxFrmCtr Register Description: MAC All Frames Transmitted Counter Register Address:

DS33Z41 Quad IMUX Ethernet Mapper 136 of 167 Register Name: SU.TxBytesCtr Register Description: MAC All Bytes Transmitted Counter Register Address

DS33Z41 Quad IMUX Ethernet Mapper 137 of 167 Register Name: SU.TxBytesOkCtr Register Description: MAC Bytes Transmitted OK Counter Register Addres

DS33Z41 Quad IMUX Ethernet Mapper 138 of 167 Register Name: SU.TXFRMUNDR Register Description: MAC Transmit Frame Under Run Counter Register Addre

DS33Z41 Quad IMUX Ethernet Mapper 139 of 167 Register Name: SU.TxBdFrmCtr Register Description: MAC All Frames Aborted Counter Register Address: 0

DS33Z41 Quad IMUX Ethernet Mapper 14 of 167 7 PIN DESCRIPTIONS 7.1 Pin Functional Description Note that all digital pins are inout pins in JTAG mo

DS33Z41 Quad IMUX Ethernet Mapper 140 of 167 10 FUNCTIONAL TIMING 10.1 MII and RMII Interfaces Each MII Interface Transmit Port has its own TX_CLK

DS33Z41 Quad IMUX Ethernet Mapper 141 of 167 Receive Data (RXD[3:0]) is clocked from the external PHY synchronously with RX_CLK. The RX_CLK signal

DS33Z41 Quad IMUX Ethernet Mapper 142 of 167 11 OPERATING PARAMETERS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Lead with Respect to VSS (excep

DS33Z41 Quad IMUX Ethernet Mapper 143 of 167 Note 1: Typical power is 145mW. Note 2: All outputs loaded with rated capacitance; all inputs betwe

DS33Z41 Quad IMUX Ethernet Mapper 144 of 167 11.2 MII Interface Table 11-5. Transmit MII Interface 10Mbps 100Mbps PARAMETER SYMBOL MIN TYP MAX MIN

DS33Z41 Quad IMUX Ethernet Mapper 145 of 167 Table 11-6. Receive MII Interface 10Mbps 100Mbps PARAMETER SYMBOL MIN TYP MAX MIN TYP MAX UNITS RX_CLK

DS33Z41 Quad IMUX Ethernet Mapper 146 of 167 11.3 RMII Interface Table 11-7. Transmit RMII Interface 10Mbps 100Mbps PARAMETER SYMBOL MIN TYP MAX MIN

DS33Z41 Quad IMUX Ethernet Mapper 147 of 167 Table 11-8. Receive RMII Interface 10Mbps 100Mbps PARAMETER SYMBOL MIN TYP MAX MIN TYP MAX UNITS REF_CL

DS33Z41 Quad IMUX Ethernet Mapper 148 of 167 11.4 MDIO Interface Table 11-9. MDIO Interface PARAMETER SYMBOL MIN TYP MAX UNITS MDC Frequency 1.

DS33Z41 Quad IMUX Ethernet Mapper 149 of 167 11.5 Transmit WAN Interface Table 11-10. Transmit WAN Interface PARAMETER SYMBOL MIN TYP MAX UNITS TCLK

DS33Z41 Quad IMUX Ethernet Mapper 15 of 167 NAME PIN TYPE FUNCTION TX_CLK A8 IO Transmit Clock (MII). Timing reference for TX_EN and TXD[3:0]. Th

DS33Z41 Quad IMUX Ethernet Mapper 150 of 167 11.6 Receive WAN Interface Table 11-11. Receive WAN Interface PARAMETER SYMBOL MIN TYP MAX UNITS RCLKI

DS33Z41 Quad IMUX Ethernet Mapper 151 of 167 11.7 SDRAM Timing Table 11-12. SDRAM Interface Timing 100MHz PARAMETER SYMBOL MIN TYP MAX UNITS SDCLKO

DS33Z41 Quad IMUX Ethernet Mapper 152 of 167 Figure 11-8. SDRAM Interface Timing SDCLKO (output) SDATA (output) t1SDATA (input)

DS33Z41 Quad IMUX Ethernet Mapper 153 of 167 Figure 11-9. Receive IBO Channel Interleave Mode Timing Note 1: 8.192MHz bus configuration. Note 2: D

DS33Z41 Quad IMUX Ethernet Mapper 154 of 167 Figure 11-10. Transmit IBO Channel Interleave Mode Timing Note 1: 8.192MHz bus configuration. Note 2:

DS33Z41 Quad IMUX Ethernet Mapper 155 of 167 11.8 Microprocessor Bus AC Characteristics Table 11-13. AC Characteristics—Microprocessor Bus Timing (

DS33Z41 Quad IMUX Ethernet Mapper 156 of 167 Figure 11-11. Intel Bus Read Timing (MODEC = 00) t2 t3Address ValidData Validt4t9t5t10ADDR[12:0]DATA[7

DS33Z41 Quad IMUX Ethernet Mapper 157 of 167 Figure 11-13. Motorola Bus Read Timing (MODEC = 01) t2 t3Address ValidData Validt4t9t5t10ADDR[12:0]DA

DS33Z41 Quad IMUX Ethernet Mapper 158 of 167 11.9 JTAG Interface Timing Table 11-14. JTAG Interface Timing (VDD3.3 = 3.3V ±5%, VDD1.8 = 1.8V ±5%, T

DS33Z41 Quad IMUX Ethernet Mapper 159 of 167 12 JTAG INFORMATION The device supports the standard instruction codes SAMPLE:PRELOAD, BYPASS, and EXTE

DS33Z41 Quad IMUX Ethernet Mapper 16 of 167 NAME PIN TYPE FUNCTION COL_DET B13 I Collision Detect (MII). Asserted by the MAC PHY to indicate tha

DS33Z41 Quad IMUX Ethernet Mapper 160 of 167 12.1 JTAG TAP Controller State Machine Description This section covers the details on the operation of

DS33Z41 Quad IMUX Ethernet Mapper 161 of 167 Update-DR A falling edge on JTCLK while in the Update-DR state will latch the data from the shift regis

DS33Z41 Quad IMUX Ethernet Mapper 162 of 167 Figure 12-2. TAP Controller State Diagram 12.2 Instruction Register The instruction register contai

DS33Z41 Quad IMUX Ethernet Mapper 163 of 167 Table 12-1. Instruction Codes for IEEE 1149.1 Architecture INSTRUCTION SELECTED REGISTER INSTRUCTION CO

DS33Z41 Quad IMUX Ethernet Mapper 164 of 167 12.3 JTAG ID Codes Table 12-2. ID Code Structure DEVICE REVISION ID[31:28] DEVICE CODE ID[27:12] MANUF

DS33Z41 Quad IMUX Ethernet Mapper 165 of 167 12.5 JTAG Functional Timing This functional timing for the JTAG circuits shows: • The JTAG controller

DS33Z41 Quad IMUX Ethernet Mapper 166 of 167 13 PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current spec

DS33Z41 Quad IMUX Ethernet Mapper 167 of 167 Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry e

DS33Z41 Quad IMUX Ethernet Mapper 17 of 167 NAME PIN TYPE FUNCTION RD/DS E1 I Read Data Strobe (Intel Mode). The DS33Z41 drives the data bus (D0-

DS33Z41 Quad IMUX Ethernet Mapper 18 of 167 NAME PIN TYPE FUNCTION SDRAM CONTROLLER SDATA[0] SDATA[1] SDATA[2] SDATA[3] SDATA[4] SDATA[5] SDATA[6

DS33Z41 Quad IMUX Ethernet Mapper 19 of 167 NAME PIN TYPE FUNCTION SCAS H4 O SDRAM Column Address Strobe. Active-low output, used to latch the co

DS33Z41 Quad IMUX Ethernet Mapper 2 of 167 TABLE OF CONTENTS 1 DESCRIPTION...

DS33Z41 Quad IMUX Ethernet Mapper 20 of 167 NAME PIN TYPE FUNCTION POWER SUPPLIES VDD3.3 G5–G10, H2, H5, H6, H7–H10 I VDD3.3: Connect to 3.3V Po

DS33Z41 Quad IMUX Ethernet Mapper 21 of 167 Figure 7-1. DS33Z41 256-Ball CSBGA Pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 A A0 A2 A5 A8 D0 D1 D2

DS33Z41 Quad IMUX Ethernet Mapper 22 of 167 8 FUNCTIONAL DESCRIPTION The DS33Z41 provides interconnection and mapping functionality between Etherne

DS33Z41 Quad IMUX Ethernet Mapper 23 of 167 8.1 Processor Interface Microprocessor control of the DS33Z41 is accomplished through the 20 interface

DS33Z41 Quad IMUX Ethernet Mapper 24 of 167 8.2 Clock Structure The DS33Z41 clocks sources and functions are as follows: • Serial Transmit Data (T

DS33Z41 Quad IMUX Ethernet Mapper 25 of 167 Figure 8-1. Clocking for the DS33Z41 MACRMIIMIISDRAMInterfaceBuffer DevDiv by 2,4,12Output Clocks25,50M

DS33Z41 Quad IMUX Ethernet Mapper 26 of 167 8.2.1 Serial Interface Clock Modes The Serial Interface timing is determined by the line clocks. 8.192

DS33Z41 Quad IMUX Ethernet Mapper 27 of 167 8.3 Resets and Low-Power Modes The external RST pin and the global reset bit in GL.CR1 create an inter

DS33Z41 Quad IMUX Ethernet Mapper 28 of 167 8.4 Initialization and Configuration EXAMPLE DEVICE INITIALIZATION SEQUENCE: STEP 1: Reset the device

DS33Z41 Quad IMUX Ethernet Mapper 29 of 167 8.7 Device Interrupts Figure 8-2 diagrams the flow of interrupt conditions from their source status bit

DS33Z41 Quad IMUX Ethernet Mapper 3 of 167 8.14 ETHERNET MAC...

DS33Z41 Quad IMUX Ethernet Mapper 30 of 167 Figure 8-2. Device Interrupt Information Flow Diagram Receive FCS Errored Packet 7Receive Aborted

DS33Z41 Quad IMUX Ethernet Mapper 31 of 167 8.8 Serial Interface The Serial Interface consists of physical serial port, IMUX/IBO Formatter, and HDL

DS33Z41 Quad IMUX Ethernet Mapper 32 of 167 Figure 8-3. IMUX Interface to T1/E1 Transceivers T1E1T1E1T1E1T1E1LIULIULIULIUFramerFramerFramerFramerIB

DS33Z41 Quad IMUX Ethernet Mapper 33 of 167 8.9.1 Microprocessor Requirements Link aggregation requires an external host microprocessor to issue in

DS33Z41 Quad IMUX Ethernet Mapper 34 of 167 8.9.2 IMUX Command Protocol The format for all commands sent and received in Channel 2 of the IBO Seria

DS33Z41 Quad IMUX Ethernet Mapper 35 of 167 The command and status registers for the IMUX function are detailed below: Table 8-4. Command and Statu

DS33Z41 Quad IMUX Ethernet Mapper 36 of 167 8.9.3 Out of Frame (OOF) Monitoring Once the links are in synchronization, frame synchronization monit

DS33Z41 Quad IMUX Ethernet Mapper 37 of 167 8.10 Connections and Queues The multi-port devices in this product family provide bidirectional cross-

DS33Z41 Quad IMUX Ethernet Mapper 38 of 167 It is recommended that the user reset the queue pointers for the connection after disconnection. The po

DS33Z41 Quad IMUX Ethernet Mapper 39 of 167 8.12 Flow Control Flow control may be required to ensure that data queues do not overflow and packets a

DS33Z41 Quad IMUX Ethernet Mapper 4 of 167 12.2.2 BYPASS...

DS33Z41 Quad IMUX Ethernet Mapper 40 of 167 8.12.1 Full-Duplex Flow Control Automatic flow control is enabled by default. The host processor can d

DS33Z41 Quad IMUX Ethernet Mapper 41 of 167 Figure 8-6. Flow Control Using Pause Control Frame Receive QueueGrowthReceive Queue HighWater MarkIniti

DS33Z41 Quad IMUX Ethernet Mapper 42 of 167 8.13 Ethernet Interface Port The Ethernet port interface allows for direct connection to an Ethernet P

DS33Z41 Quad IMUX Ethernet Mapper 43 of 167 • MII error asserted during the reception of the frame. • Dribbling bits occurred in the frame. • CR

DS33Z41 Quad IMUX Ethernet Mapper 44 of 167 Figure 8-8. Configured as DTE Connected to an Ethernet PHY in MII Mode MACRXD[3:0]RXD[3:0]RX_CLKRX_CLKR

DS33Z41 Quad IMUX Ethernet Mapper 45 of 167 Figure 8-9. DS33Z41 Configured as a DCE in MII Mode MACTXD[3:0]RXD[3:0]TX_CLKRX_CLKTX_ERRRX_ERRTX_ENRX_

DS33Z41 Quad IMUX Ethernet Mapper 46 of 167 8.14 Ethernet MAC Indirect addressing is required to access the MAC register settings. Writing to the M

DS33Z41 Quad IMUX Ethernet Mapper 47 of 167 8.14.1 MII Mode The Ethernet interface can be configured for MII operation by setting the hardware pin

DS33Z41 Quad IMUX Ethernet Mapper 48 of 167 8.14.3 PHY MII Management Block and MDIO Interface The MII Management Block allows for the host to con

DS33Z41 Quad IMUX Ethernet Mapper 49 of 167 8.15.2 Receive Data Interface 8.15.2.1 Receive Pattern Detection The Receive BERT receives only the pa

DS33Z41 Quad IMUX Ethernet Mapper 5 of 167 LIST OF FIGURES Figure 3-1. Quad T1/E1 SCT to DS33Z41 ...

DS33Z41 Quad IMUX Ethernet Mapper 50 of 167 Figure 8-13. Repetitive Pattern Synchronization State Diagram SyncMatchVerify1 bit errorPattern Matche

DS33Z41 Quad IMUX Ethernet Mapper 51 of 167 8.15.5.2 Performance Monitoring Update All counters stop counting at their maximum count. A counter reg

DS33Z41 Quad IMUX Ethernet Mapper 52 of 167 8.16 Transmit Packet Processor The Transmit Packet Processor accepts data from the Transmit FIFO perfor

DS33Z41 Quad IMUX Ethernet Mapper 53 of 167 8.17 Receive Packet Processor The Receive Packet Processor accepts data from the Receive Serial Interf

DS33Z41 Quad IMUX Ethernet Mapper 54 of 167 FCS byte extraction discards the FCS bytes. If FCS extraction is enabled, the FCS bytes are extracted f

DS33Z41 Quad IMUX Ethernet Mapper 55 of 167 8.18 X.86 Encoding and Decoding X.86 protocol provides a method for encapsulating Ethernet Frame onto

DS33Z41 Quad IMUX Ethernet Mapper 56 of 167 Figure 8-15. X.86 Encapsulation of the MAC field Flag(0x7E)Address(0x04)Control(0x03)1st Octect of SAPI

DS33Z41 Quad IMUX Ethernet Mapper 57 of 167 The X86 received frame is aborted if: • If 7d, 7E is detected. This is an abort packet sequence in X.

DS33Z41 Quad IMUX Ethernet Mapper 58 of 167 8.19 Committed Information Rate Controller The DS33Z41 provides a CIR provisioning facility. The CIR c

DS33Z41 Quad IMUX Ethernet Mapper 59 of 167 Figure 8-16. CIR in the WAN Transmit Path MACRMIIMIISDRAMInterfaceBuffer DevDiv by 2,4,12Output Clocks2

DS33Z41 Quad IMUX Ethernet Mapper 6 of 167 LIST OF TABLES Table 2-1. T1 Related Telecommunications Specifications ...

DS33Z41 Quad IMUX Ethernet Mapper 60 of 167 9 DEVICE REGISTERS Ten address lines are used to address the register space. Table 9-1 shows the regist

DS33Z41 Quad IMUX Ethernet Mapper 61 of 167 9.1 Register Bit Maps Table 9-2, Table 9-3, Table 9-4, Table 9-5, Table 9-6, and Table 9-7 contain the

DS33Z41 Quad IMUX Ethernet Mapper 62 of 167 9.1.2 Arbiter Register Bit Map Table 9-3. Arbiter Register Bit Map ADDR NAME BIT 7 BIT 6 BIT 5 B

DS33Z41 Quad IMUX Ethernet Mapper 63 of 167 9.1.4 Serial Interface Register Bit Map Table 9-5. Serial Interface Register Bit Map ADDR NAME BIT 7 B

DS33Z41 Quad IMUX Ethernet Mapper 64 of 167 ADDR NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 103h LI.RMPSCH RMX15 RMX14 RMX13 RMX12 RMX11

DS33Z41 Quad IMUX Ethernet Mapper 65 of 167 9.1.5 Ethernet Interface Register Bit Map Table 9-6. Ethernet Interface Register Bit Map ADDR NAME BIT

DS33Z41 Quad IMUX Ethernet Mapper 66 of 167 9.1.6 MAC Register Bit Map Table 9-7. MAC Indirect Register Bit Map ADDR NAME BIT 7 BIT 6 BIT 5

DS33Z41 Quad IMUX Ethernet Mapper 67 of 167 ADDR NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 110h RESERVED – initialize to FF -

DS33Z41 Quad IMUX Ethernet Mapper 68 of 167 9.2 Global Register Definitions Functions contained in the global registers include: framer reset, LIU

DS33Z41 Quad IMUX Ethernet Mapper 69 of 167 Register Name: GL.CR1 Register Description: Global Control Register 1 Register Address: 02h Bit # 7 6

DS33Z41 Quad IMUX Ethernet Mapper 7 of 167 1 DESCRIPTION The DS33Z41 provides interconnection and mapping functionality between Ethernet Packet Sys

DS33Z41 Quad IMUX Ethernet Mapper 70 of 167 Register Name: GL.RTCAL Register Description: Global Receive and Transmit Serial Port Clock Activity La

DS33Z41 Quad IMUX Ethernet Mapper 71 of 167 Register Name: GL.LIE Register Description: Global Serial Interface Interrupt Enable Register Address:

DS33Z41 Quad IMUX Ethernet Mapper 72 of 167 Register Name: GL.TRQIE Register Description: Global Transmit Receive Queue Interrupt Enable Register A

DS33Z41 Quad IMUX Ethernet Mapper 73 of 167 Register Name: GL.CON1 Register Description: Connection Register for Ethernet Interface 1 Register Addr

DS33Z41 Quad IMUX Ethernet Mapper 74 of 167 Register Name: GL.IMXCN Register Description: Inverse MUX Configuration Register Register Address: 16h

DS33Z41 Quad IMUX Ethernet Mapper 75 of 167 Register Name: GL.IMXSS Register Description: Inverse MUX Sync Status Register Address: 18h Bit # 7 6

DS33Z41 Quad IMUX Ethernet Mapper 76 of 167 Register Name: GL.IMXSLS Register Description: Inverse MUX Sync Latched Status Register Address: 1Ah

DS33Z41 Quad IMUX Ethernet Mapper 77 of 167 Register Name: GL.IMXOOFIE Register Description: Inverse MUX OOF Interrupt Enable Register Address: 1Eh

DS33Z41 Quad IMUX Ethernet Mapper 78 of 167 Register Name: GL.IMXOOFLS Register Description: Inverse MUX Out Of Frame Latched Status Register Addre

DS33Z41 Quad IMUX Ethernet Mapper 79 of 167 Bit 0: BIST Pass-Fail (BISTPF). This bit is equal to 0 after the DS33Z41 performs BIST testing on the S

DS33Z41 Quad IMUX Ethernet Mapper 8 of 167 2 FEATURE HIGHLIGHTS 2.1 General • 169-pin, 14mm x 14mm CSBGA package • 1.8V supply with 3.3V tolerant

DS33Z41 Quad IMUX Ethernet Mapper 80 of 167 Register Name: GL.SDRFTC Register Description Global SDRAM Refresh Time Control Register Address: 3Dh

DS33Z41 Quad IMUX Ethernet Mapper 81 of 167 9.3 Arbiter Registers The Arbiter manages the transport between the Ethernet port and the Serial Interf

DS33Z41 Quad IMUX Ethernet Mapper 82 of 167 9.4 BERT Registers Register Name: BCR Register Description: BERT Control Register Register Address: 80

DS33Z41 Quad IMUX Ethernet Mapper 83 of 167 Register Name: BPCLR Register Description: BERT Pattern Configuration Low Register Register Address: 82

DS33Z41 Quad IMUX Ethernet Mapper 84 of 167 Register Name: BSPB0R Register Description: BERT Pattern Byte 0 Register Register Address: 84h Bit #

DS33Z41 Quad IMUX Ethernet Mapper 85 of 167 Register Name: TEICR Register Description: Transmit Error Insertion Control Register Register Address:

DS33Z41 Quad IMUX Ethernet Mapper 86 of 167 Register Name: BSRL Register Description: BERT Status Register Latched Register Address: 8Eh Bit # 7 6

DS33Z41 Quad IMUX Ethernet Mapper 87 of 167 Register Name: RBECB0R Register Description: Receive Bit Error Count Byte 0 Register Register Address:

DS33Z41 Quad IMUX Ethernet Mapper 88 of 167 Register Name: RBCB1 Register Description: Receive Bit Count Byte 1 Register #1 Register Address: 99h

DS33Z41 Quad IMUX Ethernet Mapper 89 of 167 9.5 Serial Interface Registers The Serial Interface contains the Serial HDLC transport circuitry and t

DS33Z41 Quad IMUX Ethernet Mapper 9 of 167 2.6 SDRAM Interface • Interface for 128Mb, 32-bit-wide SDRAM • SDRAM Interface speed up to 100MHz • A

DS33Z41 Quad IMUX Ethernet Mapper 90 of 167 9.5.3 Transmit HDLC Processor Registers Register Name: LI.TPPCL Register Description: Transmit Packet

DS33Z41 Quad IMUX Ethernet Mapper 91 of 167 Register Name: LI.TIFGC Register Description: Transmit Inter-Frame Gapping Control Register Register A

DS33Z41 Quad IMUX Ethernet Mapper 92 of 167 Register Name: LI.TEPHC Register Description: Transmit Errored Packet High Control Register Register A

DS33Z41 Quad IMUX Ethernet Mapper 93 of 167 Register Name: LI.TPPSR Register Description: Transmit Packet Processor Status Register Register Addres

DS33Z41 Quad IMUX Ethernet Mapper 94 of 167 Register Name: LI.TPCR0 Register Description: Transmit Packet Count Byte 0 Register Address: 0CCh Bit

DS33Z41 Quad IMUX Ethernet Mapper 95 of 167 Register Name: LI.TBCR0 Register Description: Transmit Byte Count Byte 0 Register Address: 0D0h Bit

DS33Z41 Quad IMUX Ethernet Mapper 96 of 167 Register Name: LI.THPMUU Register Description: Serial Interface Transmit HDLC PMU Update Register Reg

DS33Z41 Quad IMUX Ethernet Mapper 97 of 167 9.5.4 X.86 Registers X.86 Transmit and common Registers are used to control the operation of the X.86 e

DS33Z41 Quad IMUX Ethernet Mapper 98 of 167 Register Name: LI.TRX86SAPIL Register Description: Transmit Receive X.86 SAPIL Register Address: 0DCh

DS33Z41 Quad IMUX Ethernet Mapper 99 of 167 9.5.5 Receive Serial Interface Serial Receive Registers are used to control the HDLC Receiver associat