Maxim DS33Z41 Instrukcja Użytkownika Pobierz pdf (Strona 8)

DS33Z41DK

8 of 44

Figure 1. System Floorplan

Figure 2 shows the DS21458 quad T1/E1 PC board floorplan. The current configuration is to populate oscillators

for MCLK1 with a 8.192MHz oscillator. Testpoints for port 3 and port 4 are provided on the WAN card, and

testpoints for ports 1 and 2 are provided on the motherboard.

Figure 2. DS21458 Resource Card Floorplan

DS33Z41 MAINBOARD

DS33Z41

SDRAM

ETHERNET PHY,

MAGNETIC,

LEDS, AND

JUMPERS

MICROPROCESSOR

AND SERIAL PORT

(57600-8-N-1)

HARDWARE

MODE SWITCHES

FOR DS33Z41

SERIAL INTERFACE

2 X 140 PIN CONNECTORS

LEDS AND TESTPOINTS

DS21458 RESOURCE CARD

(DETAIL PROVIDED BELOW)

PORT 2

PORT 4

PORT 1

PORT 3

DS21458

QUAD-PORT

T1/E1

TRANSCEIVER

140 PIN CONNECTORS

TEST POINTS

FPGA

OSC

MCLK1, 2

QUAD-PORT RJ45

QUAD

TRANSFORMER

RLOS LEDS

INT LED

1 2 3 4 5 6 7 8 9 10 11 12 13 ... 43 44

DS33Z41DK 1
Ethernet Transport Design Kit 1
TABLE OF CONTENTS 2
LIST OF FIGURES 2
LIST OF TABLES 2
COMPONENT LIST 3
4 of 44 4
5 of 44 5
6 of 44 6
Figure 1. System Floorplan 8
DS21458 8
PC BOARD ERRATA 9
FILE LOCATIONS 9
BASIC OPERATION 10
ADDRESS MAP (ALL CARDS) 14
ID REGISTERS 14
CONTROL REGISTERS 15
DOCUMENT REVISION HISTORY 16
DS33Z41 INFORMATION 16
DS33Z41DK INFORMATION 16
TECHNICAL SUPPORT 16
SCHEMATICS 17
DS33Z11/Z41 TOP LEVEL 18
PAGES 13-19 19
DS33Z11/Z41 20
DS33Z11_U3 21
SYNCHRONOUS DRAM 22
11C7v 5A5< 3D2^ 23
NC7SZ86_U 24
BLACK BLACK 25
V1_8ZCHIP 25
DP83847_U1 26
CONN_HFJ11_2450_U 27
MAX811_U 28
RESET CONFIGURATION 29
MAX3233E 30
XC2S50_BGA 31
CONN_50P_T1E1 33
DS21458 WAN INTERFACE BLOCK 35
DS21458_U 36

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Maxim DS33Z41 Instrukcja Użytkownika Strona 8

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