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DS33Z41 Quad IMUX Ethernet Mapper
30 of 167
Figure 8-2. Device Interrupt Information Flow Diagram
Receive FCS Errored Packet
7
Receive Aborted Packet
6
Receive Invalid Packet Detected
5
Receive Small Packet Detected
4
Receive Large Packet Detected
3
Receive FCS Errored Packet Count
2
Receive Aborted Packet Count
1
Receive Size Violation Packet Count
0
LI.RPPSL
LI.RPPSRIE
<Reserved>
7
<Reserved>
6
<Reserved>
5
<Reserved>
4
<Reserved>
3
<Reserved>
2
<Reserved>
1
Transmit Errored Packet Insertion Finished
0
LI.TPPSRL
LI.TPPSRIE
<Reserved>
7
<Reserved>
6
<Reserved>
5
<Reserved>
4
SAPI High is not equal to LI.TRX86SAPIH
3
SAPI Low is not equal to LI.TRX86SAPIL
2
Control is not equal to LI.TRX8C
1
Address is not equal to LI.TRX86A
0
LI.RX86S
LI.RX86LSIE
<Reserved>
7
<Reserved>
6
<Reserved>
5
<Reserved>
4
Transmit Queue FIFO Overflowed
3
Transmit Queue Overflow
2
Transmit Queue for Connection Exceeded Low Threshold
1
Transmit Queue for Connection Exceeded High
Threshold
0
LI.TQCTLS
LI.TQTIE
<Reserved>
7
<Reserved>
6
<Reserved>
5
<Reserved>
4
Receive Queue FIFO Overflowed
3
Receive Queue Overflow
2
Receive Queue for Connection Exceeded Low Threshold
1
Receive Queue for Connection Exceeded High Threshold
0
SU.QCRLS
SU.QRIE
<Reserved>
7
<Reserved>
6
<Reserved>
5
<Reserved>
4
Performance Monitor Update
3
Bit Error Detected
2
Bit Error Count
1
Out Of Synchronization
0
BSRL
BSRIE
Drawing Legend:
Interrupt Status
Registers
Register Name
Interrupt Enable
Registers
Register Name
Interrupt Pin
7
6
5
4
3
2
1
0
GL.TRQIS
GL.TRQIE
7
6
5
4
3
2
1
0
GL.LIS
GL.LIE
...
3
2
1
0
GL.SIS
GL.SIE
...
3
2
1
0
GL.IBIS
GL.IBIE
GL.IMXSLS
GL.IMXSIE
GL.IMXDFDELS
GL.IMXDFEIE
GL.IMXOOFLS
GL.IMXOOFIE
- DS33Z41 1
- Quad IMUX Ethernet Mapper 1
- TABLE OF CONTENTS 2
- LIST OF FIGURES 5
- LIST OF TABLES 6
- 1 DESCRIPTION 7
- 2 FEATURE HIGHLIGHTS 8
- 2.6 SDRAM Interface 9
- 2.7 MAC Interface 9
- 2.9 Test and Diagnostics 9
- 3 APPLICATIONS 11
- 4 ACRONYMS AND GLOSSARY 12
- 5 MAJOR OPERATING MODES 13
- 6 BLOCK DIAGRAMS 13
- 7 PIN DESCRIPTIONS 14
- 8 FUNCTIONAL DESCRIPTION 22
- 8.1 Processor Interface 23
- 8.2 Clock Structure 24
- Table 8-2. Reset Functions 27
- 8.5 Global Resources 28
- 8.6 Per-Port Resources 28
- 8.7 Device Interrupts 29
- 8.8 Serial Interface 31
- 8.9 Link Aggregation (IMUX) 31
- Sequence 01 32
- Sequence 02 32
- 8.9.2 IMUX Command Protocol 34
- 8.9.4 Data Transfer 36
- 8.10 Connections and Queues 37
- 8.11 Arbiter 38
- 8.12 Flow Control 39
- 8.13.1 DTE and DCE Mode 43
- 8.14 Ethernet MAC 46
- Figure 8-10. RMII Interface 47
- 8.15 BERT 48
- LoadVerify 49
- MatchVerify 50
- 802.3 MAC Frame 55
- Rate Adaption 55
- 9 DEVICE REGISTERS 60
- 9.1 Register Bit Maps 61
- 9.1.3 BERT Register Bit Map 62
- LI.TRX86SAPI 63
- LI.TRX86SAPIL 63
- TQOVFLS 64
- 9.1.6 MAC Register Bit Map 66
- 9.3 Arbiter Registers 81
- 9.4 BERT Registers 82
- 9.5.4 X.86 Registers 97
- 9.6.2 MAC Registers 124
- 10 FUNCTIONAL TIMING 140
- RXD[3:0] 141
- P R E A E M B L E 141
- 11 OPERATING PARAMETERS 142
- TXD[3:0] 144
- TXD[1:0] 146
- RXD[1:0] 147
- 11.7 SDRAM Timing 151
- LINK 4, CHANNEL 32 153
- LINK 1, CHANNEL 1 153
- LINK 2, CHANNEL 1 153
- Address Valid 156
- Data Valid 156
- 12 JTAG INFORMATION 159
- Capture-IR 161
- 12.2 Instruction Register 162
- 12.3 JTAG ID Codes 164
- 12.4 Test Registers 164
- 12.5 JTAG Functional Timing 165
- 13 PACKAGE INFORMATION 166
- 14 DOCUMENT REVISION HISTORY 167
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